`timescale 1ns/1ps
// -----------------------------------------------------------------------------
// Copyright (c) 2014-2023 All rights reserved
// -----------------------------------------------------------------------------
// Project Name : 
// Author 		: HiDark
// File   		: exu.sv
// Create 		: 2023-04-20 12:12:34
// Revise 		: 2023-04-20 12:12:34
// Abstract 	: 
// -----------------------------------------------------------------------------
`include "defines.svh"

module exu(
	input 	logic	[31:0]	imm ,
	input	logic			alu_srcA,	//alu operand select signal A
	input	logic	[ 1:0]	alu_srcB,	//alu operand select signal B	
	input	logic 	[ 3:0]	alu_ctrl,
	input	logic	[31:0]	PC,	
	input	logic	[31:0]	rs1_data,	
	input	logic	[31:0]	rs2_data,

	output  logic 	[31:0]	alu_out,
	output	logic			zero,	// B-type
	output	logic			less	// B-type
	);

//=================================================================================
// Signal declaration
//=================================================================================

	logic [31:0]	operand_A;
	logic [31:0]	operand_B;
//=================================================================================
// Instantiation declaration
//=================================================================================

	alu_src inst_alu_src
		(
			.alu_srcA 		(alu_srcA),
			.alu_srcB 		(alu_srcB),
			.PC        		(PC),
			.imm       		(imm),
			.rs1_data  		(rs1_data),
			.rs2_data  		(rs2_data),

			.operand_A 		(operand_A),
			.operand_B 		(operand_B)
		);

	alu_ex inst_alu_ex
		(
			.alu_ctrl  		(alu_ctrl),
			.operand_A 		(operand_A),
			.operand_B 		(operand_B),
		
			.alu_out   		(alu_out),
			.zero      		(zero),
			.less      		(less)
		);
endmodule